IDTTM/ICSTM

Low Skew Dual Bank DDR I/II Fan-out Buffer

1084C 12/03/09

ICS9P936

Low Skew Dual Bank DDR I/II Fan-out Buffer

9

Note: Bytes not shown are reserved and should not be altered.

I

2C Table: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

BUFF_IN_T/C

Frequency Detect

RW

OFF

ON

1

Bit 6

FB_OUT_T/C

FB_OUT Control

RW

Disable

Enable

1

Bit 5

DDR_T5/C5

Output Control

RW

Disable

Enable

1

Bit 4

DDR_T4/C4

Output Control

RW

Disable

Enable

1

Bit 3

DDR_T3/C3

Output Control

RW

Disable

Enable

1

Bit 2

DDR_T2/C2

Output Control

RW

Disable

Enable

1

Bit 1

DDR_T1/C1

Output Control

RW

Disable

Enable

1

Bit 0

DDR_T0/C0

Output Control

RW

Disable

Enable

1

I

2C Table: Byte Count Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

BC7

RW

0

Bit 6

BC6

RW

0

Bit 5

BC5

RW

0

Bit 4

BC4

RW

0

Bit 3

BC3

RW

1

Bit 2

BC2

RW

1

Bit 1

BC1

RW

1

Bit 0

BC0

RW

1

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

DDR_CSkw3

RW

0000 = 0

1101 = 600

0

Bit 6

DDR_CSkw2

RW

0100 = 150

1110 = 750

0

Bit 5

DDR_CSkw1

RW

1000 = 300

1111 = 900

0

Bit 4

DDR_CSkw0

RW

1100 = 450

N/A

0

Bit 3

Reserved

Reserved

RW

Reserved

Reserved

0

Bit 2

Reserved

Reserved

RW

Reserved

Reserved

0

Bit 1

FBOUTSkw1

RW

00 = 0

10 = 500

0

Bit 0

FBOUTSkw0

RW

01 = 250

11 = 750

0

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

DDR_TSkw3

RW

0000 = 0

1101 = 600

0

Bit 6

DDR_TSkw2

RW

0100 = 150

1110 = 750

0

Bit 5

DDR_TSkw1

RW

1000 = 300

1111 = 900

0

Bit 4

DDR_TSkw0

RW

1100 = 450

N/A

0

Bit 3

Reserved

Reserved

RW

Reserved

Reserved

0

Bit 2

Reserved

Reserved

RW

Reserved

Reserved

0

Bit 1

Reserved

Reserved

RW

Reserved

Reserved

0

Bit 0

Reserved

Reserved

RW

Reserved

Reserved

0

-

-

-

-

Byte 8

-

-

-

-

Byte 7

-

-

-

-

DDR_C Skew Control

(also see table1)

-

-

-

Byte Count

Programming b(7:0)

Writing to this register will

configure how many bytes

will be read back, default is

0h = 15 bytes

I

2C Table: Group Skew Control Register

Byte 19

-

-

-

-

-

-

-

-

-

FB_OUT Skew Control

(also see table 2)

I

2C Table: Group Skew Control Register

Byte 20

-

DDR_T Skew Control

(also see table1)

-

-

-

-

-

-

-