ICS9P936

IDTTM/ICSTM

Low Skew Dual Bank DDR I/II Fan-out Buffer

1084C

12/03/09

Low Skew Dual Bank DDR I/II Fan-out Buffer

DATASHEET

Description

Output Features

Dual DDR I/II fanout buffer for VIA Chipset

•

Low skew, fanout buffer

•

SMBus for functional and output control

•

Single bank 1-6 differential clock distribution

•

1 pair of differential feedback pins for input to output

synchronization

•

Supports up to 2 DDR DIMMs

•

266MHz (DDRI 533) output frequency support

•

400MHz (DDRII 800) output frequency support

•

Programmable skew through SMBus

•

Individual output control programmable through SMBus

Funtional Block Diagram

Key Specifications

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OUTPUT - OUTPUT skew: <100ps

•

Output Rise and Fall Time for DDR outputs: 650ps - 950ps

•

DUTY CYCLE: 47% - 53%

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28-pin SSOP/TSSOP package

•

RoHS compliant packaging

Pin Configuration

SCLK

SDATA

BUF_INC

BUF_INT

Control

Logic

DDRT (5:0)

DDRC (5:0)

FB_OUTC

FB_OUTT

AVDD2.5

128 GND

AGND

227 VDDQ2.5/1.8

BUF_INT

326 AVDD2.5

BUF_INC

425 AGND

DDRT0

524 DDRT5

DDRC0

623 DDRC5

DDRT1

722 GND

DDRC1

821 VDDQ2.5/1.8

GND

920 DDRT4

VDDQ2.5/1.8 10

19 DDRC4

FB_OUTT 11

18 DDRT3

FB_OUTC 12

17 DDRC3

DDRT2 13

16 SDATA

DDRC2 14

15 SCLK

28-SSOP & TSSOP