Preliminary

Preliminary Electrical Characteristics

Freescale Semiconductor

30

Figure 18. GPIO Timing

5.10 Reset and Configuration Override Timing

Figure 19. RESET and Configuration Override Timing

Table 14. Reset and Configuration Override Timing

Num

Characteristic

Symbol

Min

Max

Unit

R1

RESET Input valid to FB_CLK High

9—

ns

R2

FB_CLK High to RESET Input invalid

1.5

—

ns

R3

NOTES:

1

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to

the system. Thus, RESET must be held a minimum of 100 ns.

5—

R4

FB_CLK High to RSTOUT Valid

—10

ns

R5

RSTOUT valid to Config. Overrides valid

0—

ns

R6

Configuration Override Setup Time to RSTOUT invalid

20

—

R7

Configuration Override Hold Time after RSTOUT invalid

0—

ns

R8

RSTOUT invalid to Configuration Override High Impedance

—1

G1

FB_CLK

GPIO Outputs

G2

G3

G4

GPIO Inputs

R1

R2

FB_CLK

RESET

RSTOUT

R3

R4

R8

R7

R6

R5

Configuration Overrides*:

R4

(RCON, Override pins])