Block diagram and pin description

STLC3085

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1.3

Pin description

Table 1.

Pin description

N°

Pin

Function

1

D0

Control Interface: input bit 0.

2

D1

Control Interface: input bit 1.

3

D2

Control interface: input bit 2.

4

PD

Power Down input. Normally connected to CVCC (or to logic level high).

5

Gain SET

Control gain interface:

6,22,38,

39,40,42

NC

Not connected.

7DET

Logic interface output of the supervision detector (active low).

8

RESERVED Connected to GND

9

RESERVED Connected to GND

10

RESERVED Connected to GND

11

RESERVED Left open.

12

RESERVED Connected to GND

13

RX

4 wire input port (RX input); 300K

Ω input impedance. This signal is referred to AGND.

If connected to single supply CODEC output it must be DC decoupled with proper

capacitor.

14

ZAC1

RX buffer output (the AC impedance is connected from this node to ZAC).

15

ZAC

AC impedance synthesis.

16

RS

Protection resistors image (the image resistor is connected from this node to ZAC).

17

ZB

Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from

this node to AGND. ZA impedance is connected from this node to ZAC1).

18

CAC

AC feedback input, AC/DC split capacitor (CAC).

19

TX

4 wire output port (TX output). The signal is referred to AGND. If connected to single

supply

CODEC input it must be DC decoupled with proper capacitor.

20

CZ

Fly-Back compensation

21

VF

Feedback input for DC/DC converter controller.

23

CLK

Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or

AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally

generated and it is used instead of the external clock. When the CLK pin is connected to

AGND, the GATE output is disabled.

24

GATE

Driver for external Power MOS transistor (P-chanell in Buck-boost configuration, N-

channel in Fly-back configuration).

25

RSENSE

Voltage input for current sensing. RSENSE resistor should be connected close to this pin

and VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the

extra resistance introduced by the copper tracks.