BLP5LA55SG

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© Ampleon Netherlands B.V. 2023. All rights reserved.

Product data sheet

Rev. 1 — 7 April 2023

15 of 20

BLP5LA55SG

Power LDMOS transistor

8.

Package outline

Fig 18. Package outline TO-270-2G-1 (sheet 1 of 2)

DETAIL A

SCALE 25 : 1

A

TO-270-2G-1

Package outline drawing:

Revision:

Sheet 1 of 2

Revision date:

11/7/2022

Tolerances unless otherwise stated:

Dimension:

0.05

Angle:

1°

Third angle projection

TO-270-2G-1

0

units in mm.

4.95 (#2)

0.50

0.10

0.24

0.025

2.03

2.08

()

PIN 1

Exposed Heatsink

0.00 - 0.10

2 - 8

0.25

0.25 A

9.65 (#1)

A

7.4 min. 8.7 max.

Flash/bleed allowed

hatched area (2x)

10.67

0.10 (#4)

Compound allowed

0.20

()

#5

#5

#5

0.2 B

B