ADL5501

Rev. 0 | Page 23 of 28

EVALUATION BOARD

Figure 56 shows the schematic of the ADL5501 evaluation

board. The layout and silkscreen of the evaluation board layers

are shown in Figure 57 to Figure 60. The board is powered by

a single supply in the 2.7 V to 5.5 V range. The power supply is

decoupled by 100 pF and 0.1 μF capacitors. Table 5 details the

various configuration options of the evaluation board.

Problems caused by impedance mismatch can arise using the

evaluation board to examine the ADL5501 performance. One

way to reduce these problems is to put a coaxial 3 dB attenuator

on the RFIN SMA connector. Mismatches at the source, cable,

and cable interconnection, as well as those occurring on the

evaluation board, can cause these problems.

A simple (and common) example of such a problem is triple

travel due to mismatch at both the source and the evaluation

board. Here the signal from the source reaches the evaluation

board and mismatch causes a reflection. When that reflection

reaches the source mismatch, it causes a new reflection, which

travels back to the evaluation board, adding to the original signal

incident at the board. The resultant voltage varies with both

cable length and frequency dependence on the relative phase of

the initial and reflected signals. Placing the 3 dB pad at the input of

the board improves the match at the board and, thus, reduces

the sensitivity to mismatches at the source. When such precau-

tions are taken, measurements are less sensitive to cable length and

other fixture issues. In an actual application when the distance

between ADL5501 and source is short and well defined, this 3 dB

attenuator is not needed.

1

6

2

5

3

4

ADL5501

VPOS

FLTR

RFIN

VRMS

ENBL

COMM

C3

(OPEN)

RFIN

VRMS

R3

0Ω

R5

(OPEN)

R1

(OPEN)

VPOS

C1

100pF

C2

0.1µF

R2

(OPEN)

R4

49.9Ω

C4

100nF

TO EDGE

CONNECTOR

TO EDGE

CONNECTOR

SW1

VPOS

ENBL

Figure 56. Evaluation Board Schematic

Table 5. Evaluation Board Configuration Options

Component

Description

Default Condition

VPOS, GND

Ground and Supply Vector Pins.

Not Applicable

C1, C2

Power Supply Decoupling. The nominal supply decoupling of 100 pF and 0.1 μF.

C1 = 100 pF (Size 0402)

C2 = 0.1 μF (Size 0402)

C3

Filter Capacitor. The internal averaging capacitor can be augmented by placing additional

capacitance in C3.

C3 = Open (Size 0402)

R2, R3, C4

Output Filtering. The combination of the internal 100 Ω output resistance and C4 produce

a low-pass filter to reduce output ripple. The output can also be scaled down using the

resistor divider pads, R3 and R2. In addition, resistors and capacitors can be placed in C4 and

R2 to load test VRMS.

R2 = Open (Size 0402)

R3 = 0 Ω (Size 0402)

C4 = 100 nF (Size 0402)

R4, SW1

Device Enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS

and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded

(through the 49.9 Ω resistor), putting the device in power-down mode. While in this switch

position, the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this

case, R4 serves as a termination resistor for generators requiring a 50 Ω match.

R4 = 49.9 Ω (Size 0402)

SW1 = toward SW1 label

R1, R5

Alternate Interface. R1and R5 allow for VRMS and ENBL to be accessible from the edge

connector, which is used only for characterization.

R1 = Open (Size 0402)

R5 = Open (Size 0402)