SCM69C433 datasheet(11/24 Pages) MOTOROLA

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MCM69C433

•SCM69C433

MOTOROLA FAST SRAM

Figure 3. Connections per Second vs Match Cycle Time

MATCH DUTY CYCLE AT 66 MHz INPUT CLOCK

500

1,000

1,500

2,000

2,500

TYPICAL

WORST CASE

100

insertion and deletion is maximized if the longest–lived en-

tries are placed near the beginning of the table and the short-

est–lived entries are placed near the end of the table. For an

ATM application, this would correspond to the assignment of

small VPI values to permanent virtual circuits and large VPI

values to switched virtual circuits.

Note that at start–up, when entries are loaded into the

CAM via the fast–entry mode, the process is dominated by

the time it takes to execute the initialization instruction that

follows. The resulting effective rate of loading the CAM at

start–up is approximately 136,500 entries per second.

RESET

Asserting RESET removes all entries from the CAM table

and entry queue. The flag register is set to 1C16 (setting the

queue empty, buffered–entry mode, and table initialized bits).

The error register is set to FFFF16, indicating no errors.

Finally, the almost–full register is set to 3FFF16.

TIMING OVERVIEW

CONTROL PORT

The control port of the MCM69C433 is asynchronous.

Data transfers, both read and write, are initiated by the

assertion of the SEL signal. Address values should be valid

and WE should be high, when SEL is asserted to begin

a read cycle. All values (address, WE, and SEL) should be

held until the MCM69C433 asserts DTACK to signal the end

of the read cycle.

Address and data values should be valid and WE should

be low, when SEL is asserted to begin a write cycle. Address,

data, WE , a n d S E L values should be held until the

MCM69C433 asserts DTACK to signal the end of the write

cycle.

MATCH PORT

The MCM69C433’s match port is synchronous in opera-

tion. When the match width is

v32 bits, a match cycle can be

initiated by presenting the match data on MQ31 – MQ0 and

asserting the LH/SM signal with the appropriate setup time

relative to the rising edge of the clock. The assertion of the

MC output signifies the completion of the match cycle. If a

match has been found, the MS output is also asserted. If the

match is a virtual path circuit match in ATM mode, the VPC

output will be asserted with the MS output. Output data, if

any, is enabled by the assertion of the G input.

If the match width is greater than 32 bits, the lower bits are

first latched into the MCM69C433 by the LL input. The match

cycle is then initiated as specified in the previous paragraph.

Two alternative timing diagrams are presented to describe

the Match Port timing. In the first, LH/SM must meet setup

and hold specs across two consecutive clock cycles, while

the MQ bus need only be valid for a single cycle. In the se-

cond diagram, LH/SM need only be asserted for a single

clock cycle, while the MQ bus must be held valid with

constant data across two clock cycles.

SIMULTANEOUS PORT OPERATIONS

When the control and match ports are utilized simulta-

neously, certain procedures must be followed. If a CHECK

FOR VALUE command is issued, both the last operation

complete bit (bit 10) and the entry queue empty bit (bit 4) in

the flag register should be set prior to executing the CHECK

FOR VALUE command in order to receive valid results. How-

ever, matching on the match port can be done directly after

the last operation complete flag is set.

The match port has priority over the control port during

simultaneous operations.

DEPTH EXPANSION

Multiple CAMs can be cascaded to increase the depth of

the match table. The hardware requirements are very

straightforward, as the following pins on each device are sim-

ply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ,

DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.

Four CAMs can be easily cascaded. Simulations show that

eight devices can be cascaded if care is taken to minimize

the length of the PC board traces connecting the CAMs.

The buffered–entry mode prevents multiple matching

entries in a single CAM. The check for value instruction

should be used to verify that multiple matching entries will

not result from a potential new entry. If a match is found in

CAM 1, for example, the new value should be placed in CAM 1,

where it will replace the existing entry.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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