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FastEdge™ Series
CY2DP3110
Document #: 38-07469 Rev.*G
Page 5 of 9
Timing Definitions
VIH
VIL
VC M R
VPP
VCM R M in = VEE + 1 .2
VP P ra n g e
0.1V - 1 .3V
VCM R M a x = VCC
VC C
VEE
Figure 1. PECL/ECL Input Waveform Definitions
VI H
VI L
VX
VD I F
V C C = 3. 3V
V X m ax = 0. 9V
V X M i n = 0. 68
V D IF = > =
0. 4V m i n
VC C
VE E
V E E = 0. 0V
Figure 2. HSTL Differential Input Waveform Definitions
tr, tf,
20-80%
VO
Figure 3. ECL/LVPECL Output
VO
VP P
TP D
In p u t
Cl o c k
O u t put
Cl o c k
A n ot he r
O u t put
Cl o c k
TP L H ,
TP H L
tS K ( O )
Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O))
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
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