CY2DP3110AI datasheet(2/9 Pages) CYPRESS

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FastEdge™ Series

CY2DP3110

Document #: 38-07469 Rev.*G

Page 2 of 9

Governing Agencies

The following agencies provide specifications that apply to the

CY2DP3110. The agency name and relevant specification is

listed below in Table 2.

Pin Definitions[1, 2, 3]

Name

I/O

Type

Description

CLK_SEL

I,PD

ECL/PECL Input Clock Select.

CLKA

I,PD[1]

ECL/PECL Differential Input Clocks.

CLKA#

I,PD/PU ECL/PECL Differential Input Clocks.

5VBB

Bias

Reference Voltage Output.

CLKB,

I,PD

HSTL

Alternate Differential Input Clocks.

CLKB#

I,PD/PU

HSTL

Alternate Differential Input Clocks.

8VEE

–PWR

Power

Negative Power Supply.

1,9,16,

25,32

VCC

+PWR

Power

Positive Power Supply.

31,29,27,24,22,20,18,

15,13,11

Q(0:9)

ECL/PECL ECL/PECL Differential Output Clocks.

30,28,26,23,21,19,17,

14,12,10

Q#(0:9)

ECL/PECL ECL/PECL Differential Output Clocks.

Table 1.

Control

Operation

CLK_SEL

CLKA, CLKA# input pair is active (Default condition with no connection to pin)

CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations

CLKB, CLKB# input pair is active.

CLKB can be driven with HSTL compatible signals with respective power configurations

Table 2.

Agency Name

Specification

JEDEC

JESD 020B (MSL)

JESD 8-6 (HSTL)

JESD 51 (Theta JA)

JESD 8–2 (ECL)

JESD 65–B (skew,jitter)

Mil-Spec

883E Method 1012.1 (Thermal Theta JC)

Notes:

1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power

2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),

VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)

and are between VCC and VEE.

3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).

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