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AM29BDS643G 数据表(PDF) 39 Page - SPANSION |
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AM29BDS643G 数据表(HTML) 39 Page - SPANSION |
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39 / 49 page  May 8, 2006 25692A2 Am29BDS643G 37 D A TA SH EE T AC CHARACTERISTICS Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. Does not include the preprogramming time. Parameter Description 7G/7M 5K Unit JEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 80 45 ns tAVWL tAS Address Setup Time Min 5 4 ns tWLAX tAH Address Hold Time Min 7 6 ns tAVDP AVD# Low Time Min 12 11 ns tDVWH tDS Data Setup Time Min 45 25 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Typ 0 ns tELWL tCS CE# Setup Time Typ 0 ns tWHEH tCH CE# Hold Time Typ 0 ns tWLWH tWP/tWRL Write Pulse Width Typ 50 25 ns tWHWL tWPH Write Pulse Width High Typ 30 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 11.5 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 2, 3) Typ 0.4 sec tVPP VPP Rise and Fall Time Min 500 ns tVPS VPP Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs |
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