AM29PDL129H datasheet(35/49 Pages) SPANSION

35 / 49 page

November 2, 2005

Am29PDL129H

AC CHARACTERISTICS

CE1#/CE2# Timing

Read-Only Operations

Notes:

Not 100% tested.

See Figure 8 and Table 16 for test specifications

Valid CE1#/CE2# conditions: (CE1#= VIL, CE2#= VIH) or (CE1#=

VIH, CE2#=VIL).

Valid CE1#/CE2# transitions: (CE1#= CE2#= VIH) to (CE1#= VIL,

CE2#=VIH) or (CE1#= VIH, CE2#=VIL).

Measurements performed by placing a 50 ohm termination on the

data pin with a bias of VCC/2. The time from OE# high to the data

bus driven to VCC/2 is taken as tDF.

Valid CE1#/CE2# transitions: (CE1#= VIL, CE2#= VIH) or (CE1#=

VIH, CE2#=VIL) to (CE1#= CE2#= VIH).

For 70 pF output load capacitance, 2 ns will be added to tACC, tCE,

tPACC, tOE values for all speed options.

Parameter

Description

All Speed Options

Unit

JEDEC

Std

tCCR

CE1#/CE2# Recover Time

Min

CE1#

tCCR

CE2#

Figure 10.

Timing Diagram for Alternating Between CE1# and CE2# Control

Parameter

Description

Test Setup

Speed Options

JEDEC

Std.

Unit

tAVAV

tRC

Read Cycle Time (Note 1)

Min

tAVQV

tACC

Address to Output Delay (Note 3)

CE#, OE# = VIL

Max

55656585

tELQV

tCE

Chip Enable to Output Delay (Note 4)

OE# = VIL

Max

60657085

tPACC Page Access Time

Max

tGLQV

tOE

Output Enable to Output Delay

Max

tEHQZ

tDF

Chip Enable to Output High Z (Notes 1, 5, 6)

Max

tGHQZ

tDF

Output Enable to Output High Z (Notes 1, 5)

Max

tAXQX

tOH

Output Hold Time From Addresses, CE#/CE2#

or OE#, Whichever Occurs First (Notes 5, 6)

Min

tOEH

Output Enable Hold Time

(Note 1)

Read

Min

Toggle and

Data# Polling

Min

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