ADL5370

Rev. 0 | Page 5 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADL5370

TOP VIEW

(Not to Scale)

COM1

VPS1

COM1

VPS1

VPS1

VPS1

VPS5

VPS3

VPS4

VPS2

VPS2

VOUT

1

3

2

4

5

6

18

16

17

15

14

13

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 7, 10 to 12,

21, 22

COM1, COM2,

COM3, COM4

Input Common Pins. Connect to ground plane via a low impedance path.

3 to 6, 14 to 18

VPS1, VPS2, VPS3,

VPS4, VPS5

adequate external bypassing, connect 0.1 μF capacitors between each pin and ground. Adjacent

power supply pins of the same name can share one capacitor (see Figure 25).

19, 20, 23, 24

IBBP, IBBN, QBBN,

QBBP

Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be

dc-biased to 500 mV dc, and must be driven from a low impedance source. Nominal characterized

ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a

500 mV dc bias. These inputs are not self-biased and must be externally biased.

8, 9

LOIP, LOIN

50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled. AC-couple

LOIN to ground and drive LO through LOIP.

13

VOUT

Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the load.

Exposed Paddle

Connect to ground plane via a low impedance path.