ADA4922-1

Rev. 0 | Page 17 of 20

equations that govern the two signal paths are given in

Equation 12 and Equation 13.

(12)

(13)

When the REF voltage is set to the midswing level of the input

signal, the two output signals fall directly on top of each other

with minimal offset. Setting the REF voltage elsewhere results

in an offset between the two outputs. This effect is illustrated in

the Theory of Operation section.

The best use of the REF pin can be further illustrated by

considering a single-supply example that uses a 10 V dc power

supply and has an input signal that varies between 2 V and 7 V.

This is a case where the midswing level of the input signal is not

at midsupply but is at 4.5 V. By setting the REF input to 4.5 V

and neglecting offsets, Equation 12 and Equation 13 are used to

calculate the results. When the input signal is at its midpoint of

type of baseline state where the differential output voltage is

peak signal where the differential output voltage equals 5 V.

peak signal where the differential output voltage equals −5 V.

The resulting differential output voltage is 10 V p-p.

The previous discussion exposes how the single-ended-to-

differential gain of 2 is achieved.

INTERNAL FEEDBACK NETWORK POWER

DISSIPATION

While traditional op amps do not have on-chip feedback

elements, the ADA4922-1 contains two on-chip 600 Ω resistors

that comprise an internal feedback loop. The power dissipated

in these resistors must be included in the overall power dissipation

calculations for the device. Under certain circumstances, the

power dissipated in these resistors could be considerably more

than the device’s quiescent current. For example, on ±12 V

supplies with the REF pin tied to ground and OUT− at 9 V dc,

each 600 Ω resistor carries 15 mA and dissipates 135 mW. This

is a significant amount of power and must therefore be included

in the overall device power dissipation calculations. For ac

signals, rms analysis is required.

DISABLE FEATURE

The ADA4922-1 includes a disable feature that can be asserted

to minimize power consumption in a device that is not needed

at a particular time. When asserted, the disable feature does not

place the device output in a high impedance or three-state

condition. The disable feature is asserted by applying a control

voltage to the DIS pin and is active low. See the Specifications

section for the high and low level voltage specifications.

DRIVING A DIFFERENTIAL INPUT ADC

The ADA4922-1 provides the single-ended-to-differential

conversion that is required to drive most high resolution ADCs.

Figure 50 shows how the ADA4922-1 simplifies ADC driving.

±10V

0.1

μF

–12V

HIGH VOLTAGE

HIGH RESOLUTION

ADC

DIS

R

R

IN

8

OUT+

ADA4922-1

OUT–

4

5

6

73

REF

2

0.1

μF

–12V

0.1

μF

+12V

0.1

μF

+12V

R

R

C

C

Figure 50. Driving a Differential Input ADC

For example, consider the case where the input signal

bandwidth is 100 KHz and R = 41.2 Ω and C = 3.9 nF, as is

shown in Figure 50, to form a single-pole filter with −3 dB

bandwidth of approximately 1 MHz. The ADA4922-1 output

noise (with zero source resistance) integrated over this

bandwidth appears at the ADC input and is calculated as

()

()

rms

μV

15

MHz

1

2

π

Hz

nV/

12

)

(

,

=

⎟

⎠

⎞

⎜

⎝

⎛

=

rms

V

dm

ADC

n,

(14)

The rms value of a 20 V p-p signal at the ADC input is 7 V rms,

yielding a SNR of 113 dB at the ADC input.