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ADG2188BCPZ-R2 数据表(PDF) 7 Page - Analog Devices

部件名 ADG2188BCPZ-R2
功能描述  IC CMOS 8 횞 8 Unbuffered Analog Switch Array with Dual/Single Supplies
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADG2188BCPZ-R2 数据表(HTML) 7 Page - Analog Devices

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ADG2188
Rev. 0 | Page 7 of 28
I2C TIMING SPECIFICATIONS
VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 3.
ADG2188 Limit at TMIN, TMAX
Parameter1
Conditions
Min
Max
Unit
Description
fSCL
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
High speed mode2
CB = 100 pF maximum
3.4
MHz
CB = 400 pF maximum
1.7
MHz
t1
Standard mode
4
μs
tHIGH, SCL high time
Fast mode
0.6
μs
High speed mode2
CB = 100 pF maximum
60
ns
CB = 400 pF maximum
120
ns
t2
Standard mode
4.7
μs
tLOW, SCL low time
Fast mode
1.3
μs
High speed mode2
CB = 100 pF maximum
160
ns
CB = 400 pF maximum
320
ns
t3
Standard mode
250
ns
tSU;DAT, data setup time
Fast mode
100
ns
High speed mode2
10
ns
t43
Standard mode
0
3.45
μs
tHD;DAT, data hold time
Fast mode
0
0.9
μs
High speed mode2
CB = 100 pF maximum
0
70
ns
CB = 400 pF maximum
0
150
ns
t5
Standard mode
4.7
μs
tSU;STA, setup time for a repeated start condition
Fast mode
0.6
μs
High speed mode2
160
ns
t6
Standard mode
4
μs
tHD;STA, hold time for a (repeated) start condition
Fast mode
0.6
μs
High speed mode2
160
ns
t7
Standard mode
4.7
μs
tBUF, bus free time between a stop and a start condition
Fast mode
1.3
μs
t8
Standard mode
4
μs
tSU;STO, setup time for a stop condition
Fast mode
0.6
μs
High speed mode2
160
ns
t9
Standard mode
1000
ns
tRDA, rise time of SDA signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode2
CB = 100 pF maximum
10
80
ns
CB = 400 pF maximum
20
160
ns
t10
Standard mode
300
ns
tFDA, fall time of SDA signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode2
CB = 100 pF maximum
10
80
ns
CB = 400 pF maximum
20
160
ns



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