ADL5519ACPZ-R7 datasheet(15/27 Pages) AD

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Preliminary Technical Data

ADL5519

Rev. PrB | Page 15 of 27

POWER-DOWN INTERFACE

The operating and stand-by currents for the ADL5519 at

25°C are approximately 65 mA and 1 mA, respectively. The

PWDN and ADJ[A,B] pins are connected to the base of

and NPN transistor to force a power down condition.

Typically, when PWDN is pulled >2.5 V, the ADL5519 is

powered down from 65mA to <1mA. The output reaches

to within 0.1 dB of its steady-state value in about 1.6 μs; the

reference voltage is available to full accuracy in a much

shorter time. This wake-up response time varies depending

on the input coupling network and the capacitance at pins

CLP[A, B].

The individual log channels can be disabled by installing a

0Ω pull up resistor from ADJ[A,B] to VPS[A,B].

SETPOINT INTERFACE, VST[A, B]

The VSET input drives the high impedance (20 kΩ) input of

an internal op amp. The VSET voltage appears across the

internal 1.5 kΩ resistor to generate ISET. When a portion of

VOUT is applied to VSET, the feedback loop forces

−ID × log10(VIN/VINTERCEPT) = ISET.

If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ).

The result is

VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)

1.5k

ISET

COMM

VSET

COMM

20k

Figure 14. VST[A, B] Interface Simplified Schematic

The slope is given by –ID × 2x × 1.5 kΩ = −22 mV/dB × x. For

example, if a resistor divider to ground is used to generate a

VSET voltage of VOUT/2, then x = 2. The slope is set to −880

V/decade or −44 mV/dB.

OUTPUT INTERFACE, OUT[A, B]

The OUT[A,B] pin is driven by a PNP output stage. An

internal 10 Ω resistor is placed in series with the output and

the OUT[A,B] pin. The rise time of the output is limited

mainly by the slew on CLP[A,B]. The fall time is an RC-

limited slew given by the load capacitance and the pull-

down resistance at OUT[A,B]. There is an internal pull-

down resistor of 1.6 kΩ. A resistive load at OUT[A,B] is

placed in parallel with the internal pull-down resistor to

provide additional discharge current.

OUT[A, B]

VPS[A, B]

CLP[A,B]

1.2k

400

COMR

Figure 15. OUT[A, B] Interface Simplified Schematic

OUT[A, B] can source and sink up to 2.2 mA.

DIFFERENCE OUTPUT, OUT[P, N]

The ADL5519 incorporates two operational amplifiers with

rail-to-rail output capability to provide a channel difference

output.

OUTP

VPSR

VLVL

FBKA

COMR

OUTA

OUTB

OUTN

VPSR

VLVL

FBKB

COMR

OUTB

OUTA

Figure 16. OUT[P, N] Interface Simplified Schematic

As in the case of the output drivers for OUT[A, B], the output

stages have the capability of driving 2.2 mA. OUTA and OUTB

are internally connected through 1 kΩ resistors to the inputs of

each op amp. The pin VLVL is connected to the positive terminal

of both op amps through 1 kΩ resistors to provide level shifting.

The negative feedback terminal is also made available through a

1 kΩ resistor. The input impedance of VLVL is 1 kΩ and

FBK[A, B] is 2 kΩ. See Figure 17 for the connections of these

pins.

FBK

OUT

FBK

OUTB

OUTA

Figure 17. Op Amp Connections (All Resistors are 1 kΩ ± 20%)

If OUTP is connected to FBKA, then OUTP is given as

OUTP = OUTA – OUTB + VLVL

(9)

If OUTN is connected to FBKB, then OUTN is given as

OUTN = OUTB – OUTA + VLVL

(10)

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