CS5302

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7

PACKAGE PIN DESCRIPTION (continued)

PACKAGE PIN #

FUNCTION

PIN SYMBOL

28 Lead SO Wide

FUNCTION

PIN SYMBOL

8

N/C

No connection.

9−12

Voltage ID DAC inputs. These pins are internally pulled up to

3.3 V if left open.

13

Sets threshold for current limit. Connect to reference through

a resistive divider.

14

REF

Reference output. Decouple with 0.1 μF to LGND.

15

Power for GATE(H)2.

16

Gate(H)2

High side driver #2.

17

GND2

Return for #2 driver.

18

Gate(L)2

Low side driver #2.

19

Power for GATE(L)2.

20

SS

Soft Start capacitor pin. The Soft Start capacitor controls

both Soft Start time and hiccup mode frequency. The COMP

pin is clamped below Soft Start during Start−Up and hiccup

mode.

21

LGND

Return for internal control circuits and IC substrate connection.

22

Power for GATE(H)1. UVLO Sense for High Side Driver sup-

ply connects to this pin.

23

Gate(H)1

High side driver #1.

24

GND1

Return #1 drivers.

25

Gate(L)1

Low side driver #1.

26

Power for GATE(L)1.

27

Power for internal control circuits. UVLO Sense for Logic

connects to this pin.

28

A resistor from this pin to ground sets operating frequency