AN2533/D

Detailed Function Description

MOTOROLA

Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor)

21

The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the

parameter fault_pinstate. The parameter is placed on the A1 channel to keep

the fault channel parameter space free.

Host Interface

TPU function svmStd3Xor_fault generates an interrupt when a high to low

transition appears.

Table 18. svmStd3Xor_fault Control Bits

Name

Options

Channel Function Select

svmStd3Xor_fault function number

(Assigned during assembly the

DPTRAM code from library TPU

functions)

Channel Priority

00 – Channel Disabled

01 – Low Priority

10 – Middle Priority

11 – High Priority

Host Service Bits (HSR)

00 – No Host Service Request

01 – Not used

10 – Initialization

11 – Not used

Host Sequence Bits (HSQ)

xx – Not used

Channel Interrupt Enable

0 – Channel Interrupt Disabled

1 – Channel Interrupt Enabled

Channel Interrupt Status

0 – Interrupt Not Asserted

1 – Interrupt Asserted

Written By CPU

Written By TPU

Written by both CPU and TPU

Not Used

3

21

0

1

0

1

0

1

0

0

0

Freescale Semiconductor, Inc.

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