ADP1864

Rev. 0 | Page 13 of 16

LAYOUT CONSIDERATIONS

Layout is important with all switching regulators, but is

particularly important for high switching frequencies. Ensure

all high current paths are as wide as possible to minimize track

inductance, which causes spiking and electromagnetic inter-

ference (EMI). These paths are shown in bold in Figure 16.

Place the current sense resistor and the input capacitor(s) as

close to the IN pin as possible.

Keep the PGND connections for the diode, input capacitor(s),

and output capacitor(s) as close together as possible on a wide

PGND plane. Connect the PGND and GND planes at a single

point with a narrow trace close to the ADP1864 GND

connection.

Ensure the feedback resistors are placed as close as possible

to the FB pin to prevent stray pickup. To prevent extra noise

pickup on the FB line, do not allow the feedback trace from

the output voltage to FB to pass right beside the drain of the

external PFET. Add an extra copper plane at the connection of

the FET drain and the cathode of the diode to help dissipate the

heat generated by losses in those components.

ADP1864

COMP

GND

FB

CS

PGATE

IN

1

2

3

5

6

4

VIN

VOUT

PGND

CIN

Figure 16. Application Circuit Showing High Current Paths (in Bold)

ADP1864

VIN

PGND

VOUT

MOSFET

CIN

CO

D1

L1

RS

RFB1

RFB2

PGND

RCOMP

CCOMP

Figure 17. Example of Layout for an ADP1864 3A Application