ADP2105ACPZ-3.3-R7 datasheet(17/32 Pages) AD

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ADP2105/ADP2106/ADP2107

Rev. 0 | Page 17 of 32

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage

ripple and the loop dynamics of the converter. For a given loop

crossover frequency (the frequency at which the loop gain

drops to 0 dB), the maximum voltage transient excursion

(overshoot) is inversely proportional to the value of the output

capacitor. Therefore, larger output capacitors result in improved

load transient response. To minimize the effects of the dc-to-dc

converter switching, the crossover frequency of the compensation

loop should be less than 1/10 of the switching frequency. Higher

crossover frequency leads to faster settling time for a load transient

response, but it can also cause ringing due to poor phase

margin. Lower crossover frequency helps to provide stable

operation but needs large output capacitors to achieve competitive

overshoot specifications. Therefore, the optimal crossover

frequency for the control loop of ADP2105/ADP2106/ADP2107

is 80 kHz, 1/15 of the switching frequency. For a crossover

frequency of 80 kHz, Figure 37 shows the maximum output

voltage excursion during a 1A load transient, as the product of

the output voltage and the output capacitor is varied. Choose

the output capacitor based on the desired load transient

response and target output voltage.

OUTPUT CAPACITOR × OUTPUT VOLTAGE (μC)

Figure 37. % Overshoot for a 1 A Load Transient Response vs.

Output Capacitor × Output Voltage

For example, if the desired 1A load transient response (overshoot)

is 5% for an output voltage of 2.5 V, then from Figure 37

Output Capacitor × Output Voltage = 50 μC

≈

⇒

Capacitor

Output

The ADP2105/ADP2106/ADP2107 have been designed for

operation with small ceramic output capacitors that have low

ESR and ESL, thus comfortably able to meet tight output voltage

ripple specifications. X5R or X7R dialectrics are recommended

with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dialectrics

are not recommended, due to their poor temperature and dc

bias characteristics. Table 9 shows a list of recommended MLCC

capacitors from Murata and Taiyo Yuden.

It is also important, while choosing output capacitors, to

account for the loss of capacitance due to output voltage dc bias.

Figure 38 shows the loss of capacitance due to output voltage dc

bias for a few X5R MLCC capacitors from Murata.

–100

VOLTAGE (VDC)

–20

–40

–60

–80

246

14.7µF 0805 X5R MURATA GRM21BR61A475K

210µF 0805 X5R MURATA GRM21BR61A106K

322µF 0805 X5R MURATA GRM21BR60J226M

Figure 38. % Drop-In Capacitance vs. DC Bias for Ceramic Capacitors

(Information Provided by Murata Corporation)

For example, to get 20 μF output capacitance at an output voltage

of 2.5 V, based on Figure 38, as well as giving some margin for

temperature variance, it is suggested that a 22 μF and a 10 μF

capacitor be used in parallel to ensure that the output capacitance

is sufficient under all conditions for stable behavior.

Table 9. Recommended Input and Output Capacitor Selection

for the ADP2105/ADP2106/ADP2107

Vendor

Capacitor

Murata

Taiyo Yuden

4.7 μF 10 V

X5R 0805

GRM21BR61A475K

LMK212BJ475KG

10 μF 10 V

X5R 0805

GRM21BR61A106K

LMK212BJ106KG

22 μF 6.3 V

X5R 0805

GRM21BR60J226M

JMK212BJ226MG

INPUT CAPACITOR SELECTION

The input capacitor reduces input voltage ripple caused by the

switch currents on the PWIN pins. Place the input capacitors as

close as possible to the PWIN pins. Select an input capacitor

capable of withstanding the rms input current for the maximum

load current in your application.

For the ADP2105, it is recommended that each PWIN pin be

bypassed with a 4.7 μF or larger input capacitor. For the ADP2106,

bypass the PWIN pins with a 10 μF and a 4.7 μF capacitor, and

for the ADP2107, bypass each PWIN pin with a 10 μF capacitor.

As with the output capacitor, a low ESR ceramic capacitor is

recommended to minimize input voltage ripple. X5R or X7R

dialectrics are recommended, with a voltage rating of 6.3 V or

10 V. Y5V and Z5U dialectrics are not recommended, due to

their poor temperature and dc bias characteristics. Refer to

Table 9 for input capacitor recommendations.

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