P87LPC764FN datasheet(33/60 Pages) PHILIPS

33 / 60 page

Philips Semiconductors

Product data

P87LPC764

Low power, low price, low pin count (20 pin)

microcontroller with 4 kbyte OTP

2003 Sep 03

Serial Port Control Register (SCON)

The serial port control and status register is the Special Function

the mode selection bits, but also the 9th data bit for transmit and

receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).

The Framing Error bit (FE) allows detection of missing stop bits in

the received data stream. The FE bit shares the bit position SCON.7

with the SM0 bit. Which bit appears in SCON at any particular time

is determined by the SMOD0 bit in the PCON register. If SMOD0 =

0, SCON.7 is the SM0 bit. If SMOD0 = 1, SCON.7 is the FE bit.

Once set, the FE bit remains set until it is cleared by software. This

allows detection of framing errors for a group of characters without

the need for monitoring it for every character individually.

BIT

SYMBOL

FUNCTION

SCON.7

Framing Error. This bit is set by the UART receiver when an invalid stop bit is detected. Must be

cleared by software. The SMOD0 bit in the PCON register must be 1 for this bit to be accessible.

See SM0 bit below.

SCON.7

SM0

With SM1, defines the serial port mode. The SMOD0 bit in the PCON register must be 0 for this bit

to be accessible. See FE bit above.

SCON. 6

SM1

With SM0, defines the serial port mode (see table below).

SM0, SM1

UART Mode

Baud Rate

0 0

0: shift register

CPU clock/6

0 1

1: 8-bit UART

Variable (see text)

1 0

2: 9-bit UART

CPU clock/32 or CPU clock/16

1 1

3: 9-bit UART

Variable (see text)

SCON.5

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set

to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI

will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0.

SCON.4

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

SCON.3

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

SCON.2

RB8

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that

was received. In Mode 0, RB8 is not used.

SCON.1

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning

of the stop bit in the other modes, in any serial transmission. Must be cleared by software.

SCON.0

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through

the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by

software.

SU01157

RB8

TB8

REN

SM2

SM1

SM0/FE

SCON

Reset Value: 00h

Bit Addressable

Address: 98h

Figure 28. Serial Port Control Register (SCON)

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