Nexperia

74LVC00A

Quad 2-input NAND gate

12. Abbreviations

Table 9. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74LVC00A v.9

20210917

Product data sheet

-

74LVC00A v.8

Modifications:

• Type number 74LVC00ADB (SOT337-1/SSOP14) removed.

• Section 1 updated.

74LVC00A v.8

20200824

Product data sheet

-

74LVC00A v.7

Modifications:

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4: Derating values for Ptot total power dissipation have been updated.

• Package outline drawing of SOT762-1 (Fig. 10) updated.

74LVC00A v.7

20120425

Product data sheet

-

74LVC00A v.6

Modifications:

• Table 2: Errata in pin description corrected.

74LVC00A v.6

20120106

Product data sheet

-

74LVC00A v.5

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVC00A v.5

20030904

Product specification

-

74LVC00A v.4

74LVC00A v.4

20030507

Product specification

-

74LVC00A v.3

74LVC00A v.3

20020305

Product specification

-

74LVC00A v.2

74LVC00A v.2

19980428

Product specification

-

74LVC00A v.1

74LVC00A v.1

19970811

Product specification

-

-

74LVC00A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 9 — 17 September 2021

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