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AD8387JSVZ 数据表(PDF) 11 Page - Analog Devices |
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AD8387JSVZ 数据表(HTML) 11 Page - Analog Devices |
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11 / 16 page ![]() AD8387 Rev. 0 | Page 11 of 16 t6 t2 t1 t4 t3 CLK DB(0:11) XFR VTH VTH VTH t1 t2 t5 Figure 15. Input Timing (DSW = LOW) DB(0:11) XFR INV VID(0:11) t8 VRL 50% VRL VRL + VFS VRL–VFS CLK –2 15 t7 t7 PIXELS –12, –11, –10, –9, –8, –7, –6, –5, –4, –3, –2, –1 PIXELS 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 –1 1 2 3 4 5 6 7 8 9 10 11 13 14 12 0 Figure 16. Output Timing (DSW = LOW) Table 4. Parameter Conditions Min Typ Max Unit Data Setup Time: t1 0 ns XFR Setup Time: t3 0 ns Data Hold Time: t2 3.5 ns XFR Hold Time: t4 3.5 ns CLK High Time: t5 DSW = HIGH 2.5 ns CLK Low Time: t6 DSW = HIGH 3.0 ns CLK High Time: t7 DSW = LOW 3.5 ns CLK Low Time: t8 DSW = LOW 4.0 ns Data Switching Delay: t7 15.7 ns Data Switching Delay Skew: Δt7 VIDx = 5 V step 4 ns Invert Switching Delay: t8 16.2 ns Invert Switching Delay Skew: Δt8 4 ns |
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