AD9514

Rev. 0 | Page 10 of 28

SYNCB, VREF, AND SETUP PINS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYNCB

Logic High

2.7

V

Logic Low

0.40

V

Capacitance

2

pF

VREF

Output Voltage

V

Minimum − maximum from 0 mA to 1 mA load

S0 TO S10

Levels

0

V

1/3

V

2/3

V

1

V

POWER

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-ON SYNCHRONIZATION1

35

ms

See Figure 24.

POWER DISSIPATION

295

405

550

mW

All outputs on. 2 LVPECL (divide = 2), 1 LVDS (divide = 2). No clock.

Does not include power dissipated in external resistors.

380

490

635

mW

All outputs on. 2 LVPECL (divide = 2), 1 CMOS (divide = 2);

at 62.5 MHz out (5 pF load).

410

525

680

mW

All outputs on. 2 LVPECL, 1 CMOS (divide = 2); At 125 MHz out (5 pF load).

POWER DELTA

Divider (Divide = 2 to Divide = 1)

15

30

45

mW

For each divider. No clock.

LVPECL Output

65

90

125

mW

For each output. No clock.

LVDS Output

20

50

85

mW

No clock.

CMOS Output (Static)

30

40

50

mW

No clock.

CMOS Output (@ 62.5 MHz)

80

110

140

mW

Single-ended. At 62.5 MHz out with 5 pF load.

CMOS Output (@ 125 MHz)

110

150

190

mW

Single-ended. At 125 MHz out with 5 pF load.

Delay Block

30

45

65

mW

Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.

transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.