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AD9514/PCB 数据表(PDF) 21 Page - Analog Devices

部件名 AD9514/PCB
功能描述  1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9514/PCB 数据表(HTML) 21 Page - Analog Devices

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Rev. 0 | Page 21 of 28
Table 13. S5, S6—OUT2 Divide or OUT1 Phase
S2 ≠ 0
S2 = 0
S5
S6
OUT2
Divide (Duty Cycle1)
OUT1
Phase
0
0
1
0
1/3
0
2 (50%)
1
2/3
0
3 (33%)
2
1
0
4 (50%)
3
0
1/3
5 (40%)
4
1/3
1/3
6 (50%)
5
2/3
1/3
8 (50%)
6
1
1/3
9 (44%)
7
0
2/3
10 (50%)
8
1/3
2/3
12 (50%)
9
2/3
2/3
15 (47%)
10
1
2/3
16 (50%)
11
0
1
18 (50%)
12
1/3
1
24 (50%)
13
2/3
1
30 (50%)
14
1
1
32 (50%)
15
1 Duty cycle is the clock signal high time divided by the total period.
Table 14. S7, S8—OUT1 Divide or OUT2 Phase
S2 ≠ 1
S2 = 1 and S0 ≠ 0
S7
S8
OUT1
Divide (Duty Cycle1)
OUT2
Phase
0
0
1
0
1/3
0
2 (50%)
1
2/3
0
3 (33%)
2
1
0
4 (50%)
3
0
1/3
5 (40%)
4
1/3
1/3
6 (50%)
5
2/3
1/3
8 (50%)
6
1
1/3
9 (44%)
7
0
2/3
10 (50%)
8
1/3
2/3
12 (50%)
9
2/3
2/3
15 (47%)
10
1
2/3
16 (50%)
11
0
1
18 (50%)
12
1/3
1
24 (50%)
13
2/3
1
30 (50%)
14
1
1
32 (50%)
15
1 Duty cycle is the clock signal high time divided by the total period.
Table 15. S9, S10—OUT0 Divide or OUT2 Divide
S2 ≠ 2/3
S2 = 2/3
S9
S10
OUT0
Divide (Duty Cycle1)
OUT2
Divide (Duty Cycle1)
0
0
1
7 (43%)
1/3
0
2 (50%)
11 (45%)
2/3
0
3 (33%)
13 (46%)
1
0
4 (50%)
14 (50%)
0
1/3
5 (40%)
17 (47%)
1/3
1/3
6 (50%)
19 (47%)
2/3
1/3
8 (50%)
20 (50%)
1
1/3
9 (44%)
21 (48%)
0
2/3
10 (50%)
22 (50%)
1/3
2/3
12 (50%)
23 (48%)
2/3
2/3
15 (47%)
25 (48%)
1
2/3
16 (50%)
26 (50%)
0
1
18 (50%)
27 (48%)
1/3
1
24 (50%)
28 (50%)
2/3
1
30 (50%)
29 (48%)
1
1
32 (50%)
31 (48%)
1 Duty cycle is the clock signal high time divided by the total period.



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