AD9880SLASHPCB datasheet(22/64 Pages) AD

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AD9880

Rev. 0 | Page 22 of 64

DATAIN

P10

P11

HSIN

DATACLK

8 CLOCK CYCLE DELAY

DATAOUT

2 CLOCK CYCLE DELAY

HSOUT

Figure 15. RGB ADC Timing

DATAIN

P10

P11

HSIN

DATACLK

8 CLOCK CYCLE DELAY

CB/CROUT

YOUT

2 CLOCK CYCLE DELAY

1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.

2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT.

HSOUT

Figure 16. YCrCb ADC Timing

Table 10.

Port

Red

Green

Blue

Bit

4:4:4

Red/Cr [7:0]

Green/Y [7:0]

Blue/Cb [7:0]

4:2:2

CbCr [7:0]

Y [7:0]

DDR 4:2:2 ↑ CbCr ↓ Y,Y

DDR ↑ 1 G [3:0]

DDR ↑ B [7:4]

DDR ↑ B [3:0]

DDR 4:2:2 ↑ CbCr [11:0]

4:4:4 DDR

DDR ↓ R [7:0]

DDR ↓ G [7:4]

DDR 4:2:2 ↓ Y,Y [11:0]

4:2:2-12

CbCr [11:0]

Y [11:0]

1 Arrows in the table indicate clock edge. Rising edge of clock =

↑, falling edge = ↓.

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