FXPS7115D4S datasheet(39/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.7.1 Data source enable bits (SIDx_EN)

The SIDx_EN are control bits for both I2C and SPI modes. In I2C mode, they configure the automatic register

read wrap-around feature to optimize the number of I2C transactions. See Section 7.4.6.3 and Table 9 for

details.

In SPI mode, the SIDx_EN bits enable and map the data source (SNSDATA0, SNSDATA1) to the associated

source identification as described in Table 11. Additionally, the SPI error response monitoring can be mapped to

the SOURCEID_x channels. SPI error responses are detailed in Section 7.5.4 "Error checking".

Source ID

Source ID Enable (SIDx_EN)

Transmitted data

SPI error response

SOURCEID_0

SNSDATA0

SPI error response

SOURCEID_1

SNSDATA1

Table 57. Source ID enable

In I2C mode, the SOURCEID_x registers are readable and writable but have no effect on the device. See

Table 11, for details regarding the effect of the SIDx_EN bits.

7.7.8 SPI Configuration Control Register (SPI_CFG, Address 3Dh)

In SPI mode, the SPI configuration control register is a user programmed read/write register that contains the

SPI protocol configuration information. This register is included in the read/write array error detection. This

Bit

Symbol

reserved

DATASIZE

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

Factory default

Access

R/W

Table 58. SPI_CFG Register (address 3Dh) bit allocation

7.7.8.1 SPI Data Field Size (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 59.

DATASIZE

SPI Data Field Size

12-Bits

16-Bits

Table 59. DATASIZE Bit Definition

7.7.8.2 SPI CRC Length and Seed Bits

The SPI_CRC_LEN[1:0] bits select the CRC length for SPI Mode as shown in the table below. The SPI

CRC seed bits contain the seed used for the SPI Mode. The default SPI CRC is an 8-bit. When the

SPI_CRC_LEN[1:0] bits are set to a non-zero value using a Register Write command, the SPI CRC changes

as defined in the table. The new polynomial value is enabled for both MISO and MOSI on the next SPI Mode

command. The default seed (SPICRCSEED[3:0] = 0h) is FFh for an 8-bit CRC. When the value is changed to

a non-zero value using a Register Write command, the SPI CRC seed changes to the value programmed as

shown in the table. The new seed value is enabled for both MISO and MOSI on the next SPI Mode command.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1.2 — 28 June 2023

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