MC44BS374T1/374T1A Advance Information

High Speed I2C Compatible Bus

17.3 Level Definitions

SDA/SCL high and low levels are designed to be compatible with 0-5V and 0-3.3V SDA / SCL signals.

Figure 11. SDA/SCL Levels

In write mode, each ninth data bit (bits 9, 18, 27, 36, and 45) is an acknowledge bit (ACK) during which

the MCU sends a logic 1 and the Modulator circuit answers on the data line by pulling it low. Besides the

chip address, the circuit needs two or four data bytes for operation. The following sequences of data bytes

are the permitted incoming information:

1 1 0 0 1 0 1 0 (ACK) = $CA (hex) in write mode

Table 10. Permitted Data Bytes (Incoming Information)

Example 1

STA

CA

C1

C0

STO

Example 2

STA

CA

FM

FL

STO

Example 3

STA

CA

C1

C0

FM

FL

STO

Example 4

STA

CA

FM

FL

C1

C0

STO

Note:

STA = Start condition

CA = Chip Address

SDA

...

0V

Vcc

Vih

Vil

dead band

1

2

3

4

5

6

7

8

9 10

14

11 12 13

45

44

15

19

16 17 18

STA

Chip Address ($CA)

ACK

ACK

First Data Byte (C1 or FM)

Data

ACK

Stop

SCL

SDA

Freescale Semiconductor, Inc.

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