CD54AC109, CD74AC109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS326 – JANUARY 2003

2

POST OFFICE BOX 655303

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

J

K

Q

Q

L

H

X

X

X

H

L

H

LX

X

X

L

H

L

LX

X

X

H†

H†

H

H

↑

LL

L

H

H

H

↑

H

L

Toggle

H

H

↑

LH

Q0

Q0

H

H

↑

HH

H

L

H

H

L

X

X

Q0

Q0

† Unpredictable and unstable condition if both PRE and CLR

go low simultaneously

logic diagram, each flip-flop (positive logic)

PRE

CLK

J

CLR

Q

Q

C

C

C

C

K

TG

TG

TG

TG

C

C

C

C

C

C