PEMD2_PIMD2_PUMD2

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 8 — 14 November 2013

3 of 18

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 k

, R2 = 22 k

5.

Limiting values

[1]

Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor; for the PNP transistor with negative polarity

VCBO

collector-base voltage

open emitter

-

50

V

VCEO

collector-emitter voltage

open base

-

50

V

VEBO

emitter-base voltage

open collector

-

10

V

VI

input voltage TR1

positive

-

+40

V

negative

-

10

V

input voltage TR2

positive

+10

negative

40

IO

output current

-

100

mA

ICM

peak collector current

single pulse;

tp  1ms

-100

mA

Ptot

total power dissipation

Tamb  25 C

PEMD2 (SOT666)

[1] -200

mW

PIMD2 (SOT457)

[1]

250

mW

PUMD2 (SOT363)

[1] -200

mW

Per device

Ptot

total power dissipation

Tamb  25 C

PEMD2 (SOT666)

[1] -300

mW

PIMD2 (SOT457)

[1]

400

mW

PUMD2 (SOT363)

[1] -300

mW

Tj

junction temperature

-

150

C

Tamb

ambient temperature

55

+150

C

Tstg

storage temperature

65

+150

C