数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

M16C/62 数据表(PDF) 41 Page - Renesas Technology Corp

部件名 M16C/62
功能描述  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PDF  87 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M16C/62 数据表(HTML) 41 Page - Renesas Technology Corp

Back Button M16C/62 Datasheet HTML 37Page - Renesas Technology Corp M16C/62 Datasheet HTML 38Page - Renesas Technology Corp M16C/62 Datasheet HTML 39Page - Renesas Technology Corp M16C/62 Datasheet HTML 40Page - Renesas Technology Corp M16C/62 Datasheet HTML 41Page - Renesas Technology Corp M16C/62 Datasheet HTML 42Page - Renesas Technology Corp M16C/62 Datasheet HTML 43Page - Renesas Technology Corp M16C/62 Datasheet HTML 44Page - Renesas Technology Corp M16C/62 Datasheet HTML 45Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 87 page
background image
M16C/62 Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
o
3
0
0
2
,
7
0
.
v
o
N
0
1
.
2
.
v
e
R
page 41
Table 5.27 Memory Expansion and Microprocessor Modes (for setting with no wait)
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Symbol
Standard
Measuring condition
Max.
Min.
ParameterUnit
td(BCLK-AD)
Address output delay time25ns
th(BCLK-AD)
Address output hold time (refers to BCLK)4
ns
th(BCLK-CS)
Chip select output hold time (refers to BCLK)4
ns
td(BCLK-ALE)
ALE signal output delay time
15
ns
th(BCLK-ALE)
ALE signal output hold time
–4
ns
td(BCLK-RD)
RD signal output delay time25ns
th(BCLK-RD)
RD signal output hold time0
ns
td(BCLK-WR)
WR signal output delay time25ns
th(BCLK-WR)
WR signal output hold time0
ns
td(BCLK-DB)
Data output delay time (refers to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (refers to BCLK)(3)
4ns
th(WR-DB)
Data output hold time (refers to WR)(3)
ns
td(DB-WR)
Data output delay time (refers to WR)
ns
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
– 40
[ns]
td(BCLK-CS)
Chip select output delay time25ns
th(RD-AD)
Address output hold time (refers to RD)0
ns
th(WR-AD)
Address output hold time (refers to WR)
(Note 2)
ns
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1k
Ω, hold time
of output “L” level is
t = – 30pF X 1k
Ω X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.
DBi
R
C
(Note 1)
(Note 2)
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
f(BCLK) is 12.5MHz or less.
– 10
NOTES:
HLDA output delay time
40
ns
td(BCLK-HLDA)
See Figure 5.1
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
P11
P12
P13
P14
Figure 5.1 Ports P0 to P14 Measurement Circuit



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com