GWIXC1100BDT datasheet(27/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

• Eight-entry write buffer allows the core to continue execution while data is written to memory

• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with

40-bit accumulation for efficient, high-quality media and signal processing

• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle

counter for analysis of hit rates, etc.

This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of

internal bus performance.

• JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-

change messages) to debug programs

2.2.1

Super Pipeline

The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes.

The integer pipe has seven stages:

• Branch Target Buffer (BTB)/Fetch 1

• Fetch 2

• Decode

• Register File/Shift

• ALU Execute

• State Execute

• Integer Writeback

Figure 6.

Intel XScale® Core Block Diagram

A9568-02

Multiply

Accumulate

Execution

Core

Interrupt

Request

Instruction

FIQ

Coprocessor Interface

IRQ

Data

Address

Data

System

Management

Debug/

PMU

JTAG

South

AHB

Bus

Data Cache

32 KB

Mini-Data Cache

2 KB

Instruction Cache

32 KB

Branch Target Cache

GWIXC1100BDT 数据表(PDF) 27 Page - Intel Corporation

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