GWIXC1100BDT datasheet(48/134 Pages) INTEL

48 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

Table 18.

System Interface††

Name

Power

Reset1

Reset2

Type†

Description

BYPASS_CLK

Used for test purposes only.

Must be pulled high for normal operation.

SCANTESTMODE_N

VI/PE

Used for test purposes only.

Must be pulled high for normal operation.

RESET_IN_N

Used as a reset input to the device after power up

conditions have been met. Power up conditions include

the power supplies reaching a safe stable condition and

the PLL achieving a locked state and the

PWRON_RESET_N coming to an active state prior to

the RESET_IN_N coming to an active state.

PWRON_RESET_N

Signal used at power up to reset all internal logic to a

known state after the PLL has achieved a locked state.

The PWRON_RESET_N input is a 1.3-V tolerant only.

HIGHZ_N

VI/PE

Used for test purposes only.

Must be pulled high for normal operation.

PLL_LOCK

Signal used to inform external reset logic that the

internal PLL has achieved a locked state.

RCOMP

Signal used to control PCI drive strength characteristics.

Drive strength is varied on PCI address, data and

control signals.

Pin requires a 34-

Ω +/- 1% tolerance resistor to ground.

Refer to Figure 13 on page 85.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

††

IMPORTANT NOTE: When a system-level reset is asserted to the Intel® IXP42X Product Line of

Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system

reset, or a Watchdog-Timer reset — and any interface is in an active transaction (particularly the PCI

bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior

of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a

reset of other attached devices may be required.

Table 19.

Power Interface (Sheet 1 of 2)

Name

Type†

Description

VCC

1.3-V power supply input pins used for the internal logic.

VCCP

3.3-V power supply input pins used for the peripheral (I/O) logic.

VSS

Ground power supply input pins used for both the 3.3-V and the 1.3-V power supplies.

VCCOSCP

3.3-V power supply input pins used for the peripheral (I/O) logic of the analog

oscillator circuitry.

Require special power filtering circuitry. Refer to Figure 11 on page 84

VSSOSCP

Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry.

Used in conjunction with the VCCOSCP pins.

Requires special power filtering circuitry. Refer to Figure 11 on page 84

†

For a legend of the Type codes, see Table 5 on page 33.

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