Nexperia

74HC3G34-Q100; 74HCT3G34-Q100

Triple buffer gate

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Figure 5.  Test circuit for measuring switching times

Table 10. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPHL, tPLH

74HC3G34-Q100

GND to VCC

≤ 6 ns

50 pF

1 kΩ

open

74HCT3G34-Q100 GND to 3 V

≤ 6 ns

50 pF

1 kΩ

open

74HC_HCT3G34_Q100

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© Nexperia B.V. 2018. All rights reserved.

Product data sheet

Rev. 2 — 11 June 2018

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