STV0672 datasheet(6/105 Pages) STMICROELECTRONICS

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VV5410 & VV6410

Introduction

cd5410-6410f-3-0.fm

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2.3.1

Digital Data Bus

Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the

video data stream to allow a co-processor to synchronise with video data the camera module is generating. Section 8. defines the

format for the output video data stream.

2.3.2

Frame Grabber Control Signals

To complement the embedded control sequences the data qualification clock (QCK), the line start signal (LST) and the field start

signal (FST) signals can be independently set-up as follows:

1. Disabled

2. Free-running.

3. Qualify only the control sequences and the pixel data.

4. Qualify the pixel data only

There is also the choice of two different QCK frequencies where one is twice the frequency of the other.

1. Fast QCK: the falling edge of the clock qualiﬁes every 8, 5 or 4 bit blocks of data that makes up a pixel value.

2. Slow QCK: the rising edge qualiﬁes 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge quali-

ﬁes the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode the rising edge of the clock qualiﬁes the most signiﬁ-

cant nibbles while the falling edge of the clock qualiﬁes the least signiﬁcant nibbles.

2.3.3

2-wire Serial Interface

The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses

are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written

to in parallel.

Section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed

via the serial interface.

Figure 1 : Block Diagram of VV5410/VV6410 Image Sensor (5-wire output)

OUTPUT

FORMAT

D[4:0]

QCK

LST

FST

SDA

SCL

OEB

CLKI

RESETB

IMAGE

FORMAT

EXPOSURE

CONTROL

SERIAL

INTERFACE

OFFSET

CANCELLATION

Digital Logic

Y-

DECODER

VREGS,

AUDIO AMP.,

& REFS

PHOTO DIODE

ARRAY

Column ADC

Readout

Analogue Core

Structure

X-Decoder

SRAM line store

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