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STV0672 数据表(PDF) 5 Page - STMicroelectronics |
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STV0672 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 105 page ![]() CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000 VV5410 & VV6410 Commercial in confidence 5/105 cd5410-6410f-3-0.fm 2. Introduction 2.1 Overview VV5410/VV6410 is a CIF format CMOS image sensor. The VV5410 sensor is the basic monochrome device and VV6410 is the colourised variant. The operation of VV5410 and VV6410 is very similar but any differences will be identified and explained. VV6410 can output digital colourised pixel data at frame and line rates compatible with either NTSC or PAL video standards. VV5410 and VV6410 contain the same basic video timing modes. Table 2 summarises these video modes. The various operating modes are detailed in Section 3. Important: VV5410 and VV6410’s output video data stream only contains raw data. A master co-processor is required to generate a video waveform that can be displayed on a VDU Note: The user can also provide a 24 MHz clock, rather than a 16 MHz clock, for the QCIF-60fps, CIF-25fps and CIF-30fps modes, which the sensor then internally divides by 1.5, (see data_format[22]), to give an effective input clock frequency of 16 MHz. 2.2 Exposure Control VV5410/VV6410 does not include any form of automatic exposure and/or gain control. Thus to produce a correctly exposed image the integration period for the pixels, in the sensor array, an exposure control algorithm must be implemented externally. The new exposure values are written to the sensor via the serial interface. 2.3 Digital Interface The sensor’s offers a very flexible digital interface, the main components of which are listed below: 1. A tri-stateable 5-wire data bus (D[4:0]) for sending both video data and embedded timing references. 2. 4-wire and 8-wire data bus alternatives available. If the 8-wire option is selected then the FST/LST pins are reconfigured to output data information. 3. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of different ways (Tri-stateable). 4. A line start signal, LST (Tri-stateable). 5. A frame start signal, FST (Tri-stateable). 6. OEB tri-states all 5 data bus lines, D[4:0], the qualification clock, QCK, LST, FST and D[7]. 7. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device. Mode Input Clock (MHz)Note System Clock Divisor Image Size Line Time ( µs) Lines per Frame Frame Rate (fps) QCIF - 25 fps 8.00 8 180 x 148 250.00 160 25.00000 QCIF - 30 fps 8.00 8 180 x 148 208.00 160 30.04807 QCIF - 60 fps 16.00 8 180 x 148 104.00 160 60.09614 CIF - 25 fps 16.00 4 356 x 292 125.00 320 25.00000 CIF - 30 fps 16.00 4 356 x 292 104.00 320 30.04807 NTSC (3.2 fsc) 28.636360 / 2.5 2 306 x 244 63.555564 525 29.97003 PAL (3.2 fsc) 35.46895 / 2.5 2 356 x 292 63.999639 625 25.00014 Table 2 : Video Modes |
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