MCP3421 datasheet(8/30 Pages) MICROCHIP

8 / 30 page

MCP3421

DS22003B-page 8

The output codes will not roll-over if the input voltage

exceeds the maximum input range. In this case, the

code will be locked at 0111...11 for all voltages

greater than +(VREF - 1 LSB) and 1000...00 for

voltages less than -VREF. Table 4-2 shows an example

of output codes of various input levels using 18 bit

conversion mode. Table 4-3 shows an example of

minimum and maximum codes for each data rate

option.

The output code is given by:

EQUATION 4-1:

The LSB of the code is given by:

EQUATION 4-2:

TABLE 4-1:

LSB SIZE OF VARIOUS BIT

CONVERSION MODES

TABLE 4-2:

EXAMPLE OF OUTPUT CODE

FOR 18 BITS

TABLE 4-3:

MINIMUM AND MAXIMUM

CODES

4.6

Self-Calibration

The device performs a self-calibration of offset and

gain for each conversion. This provides reliable

conversion results from conversion-to-conversion over

variations in temperature as well as power supply

fluctuations.

4.7

Input Impedance

The MCP3421 uses a switched-capacitor input stage

using a 3.2 pF sampling capacitor. This capacitor is

switched (charged and discharged) at a rate of the

sampling frequency that is generated by the on-board

clock. The differential mode impedance varies with the

PGA settings. The typical differential input impedance

during a normal mode operation is given by:

Since the sampling capacitor is only switching to the

input pins during a conversion process, the above input

impedance is only valid during conversion periods. In a

low power standby mode, the above impedance is not

presented at the input pins. Therefore, only a leakage

current due to ESD diode is presented at the input pins.

The conversion accuracy can be affected by the input

signal source impedance when any external circuit is

connected to the input pins. The source impedance

adds to the internal impedance and directly affects the

time required to charge the internal sampling capacitor.

Therefore, a large input source impedance connected

to the input pins can increase the system performance

errors such as offset, gain, and integral nonlinearity

(INL) errors. Ideally, the input source impedance

should be zero. This can be achievable by using an

operational amplifier with a closed-loop output

impedance of tens of ohms.

Bit Resolutions

LSB (V)

12 bits

1 mV

14 bits

250 µV

16 bits

62.5 µV

18 bits

15.625 µV

Input Voltage (V)

Digital Code

≥

VREF

011111111111111111

VREF - 1 LSB

011111111111111111

2LSB

000000000000000010

1LSB

000000000000000001

000000000000000000

-1 LSB

111111111111111111

-2 LSB

111111111111111110

- VREF

100000000000000000

< -VREF

100000000000000000

Output Code

Max Code 1

()

VIN+VIN-

–

()

2.048V

---------------------------------------

LSB

2 2.048V

--------------------------

Where:

N = the number of bits

Number

of Bits

Data Rate

Minimum

Code

Maximum

Code

240 SPS

-2048

2047

60 SPS

-8192

8191

15 SPS

-32768

32767

3.75 SPS

-131072

131071

Note:

Maximum n-bit code = 2n-1 - 1

Minimum n-bit code = -1 x 2n-1

ZIN(f) = 2.25 MΩ/PGA

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