© 2006 Microchip Technology Inc.

DS22003B-page 13

MCP3421

FIGURE 5-1:

MCP3421 Address Byte.

5.3.2

READING DATA FROM THE DEVICE

When the Master sends a read command (R/W = 1),

the MCP3421 outputs the conversion data bytes and

configuration byte. Each byte consists of 8 bits with

one acknowledge (ACK) bit. The ACK bit after the

address byte is issued by the MCP3421 and the ACK

bits after each conversion data bytes are issued by the

Master.

When the device is configured for 18-bit conversion

mode, the device outputs three data bytes followed by

a configuration byte. The first 7 data bits in the first

data byte are the MSB of the conversion data. The

user can ignore the first 6 data bits, and take the 7th

data bit (D17) as the MSB of the conversion data. The

LSB of the 3rd data byte is the LSB of the conversion

data (D0).

If the device is configured for 12, 14, or 16 bit-mode, the

device outputs two data bytes followed by a

configuration byte. In 16 bit-conversion mode, the MSB

of the first data byte is the MSB (D15) of the conversion

data. In 14-bit conversion mode, the first two bits in the

first data byte can be ignored (they are the MSB of the

conversion data), and the 3rd bit (D13) is the MSB of

the conversion data. In 12-bit conversion mode, the

first four bits can be ignored (they are the MSB of the

conversion data), and the 5th bit (D11) of the byte

represents the MSB of the conversion data. Table 5-3

shows an example of the conversion data output of

each conversion mode.

The configuration byte follows the output data byte.

The device outputs the configuration byte as long as

the SCL pulses are received. The device terminates

the current outputs when it receives a Not-Acknowl-

edge (NAK), a repeated start or a stop bit at any time

during the output bit stream. It is not required to read

the configuration byte. However, the user may read the

configuration byte to check the RDY bit condition to

confirm whether the just received data bytes are

updated conversion data. The user may continuously

send clock (SCL) to repeatedly read the configuration

bytes to check the RDY bit status.

Figures 5-2 and 5-3 show the timing diagrams of the

reading.

5.3.3

WRITING A CONFIGURATION BYTE

TO THE DEVICE

When the Master sends an address byte with the R/W

bit low (R/W = 0), the MCP3421 expects one

configuration byte following the address. Any byte sent

after this second byte will be ignored. The user can

change the operating mode of the device by writing the

configuration register bits.

If the device receives a write command with a new

configuration setting, the device immediately begins a

new conversion and updates the conversion data.

Start bit

Read/Write bit

Address Byte

R/W ACK

1

1

0

1

X

X

X

Device Code

Address

Acknowledge bit

Address

Note 1:

Specified by customer and programmed at the

factory. If not specified by the customer,

programmed to ‘

TABLE 5-3:

EXAMPLE OF CONVERSION DATA OUTPUT OF EACH CONVERSION MODE

Conversion

Mode

Conversion Data Output

18-bits

MMMMMMMD16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration

byte

16-bits

MD14~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

14-bits

MMMD12~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

12-bits

MMMMMD10D9D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte

Note:

M is MSB of the data byte.