5

VP7615

Pin #

I/O

Name

Description

60

In*

CPCKA

Clock - This input receives the clock from the CamPort™ camera on port A.

54

In*

CPDA3

CamPort™ Data Bit 3 - This bus receives the data from the CamPort™ camera on port

A.

55

In*

CPDA2

CamPort™ Data Bit 2 - Port A

56

In*

CPDA1

CamPort™ Data Bit 1 - Port A

59

In*

CPDA0

CamPort™ Data Bit 0 - Port A

88

In*

CPCKB

CamPort™ B Clock - This input receives the clock from the CamPort™ camera on port

B.

84

In*

CPDB3

CamPort™ B Data Bit 3 - This bus receives the data from the CamPort™ camera on

port B.

85

In*

CPDB2

CamPort™ B Data Bit 2

86

In*

CPDB1

CamPort™ B Data Bit 1

87

In*

CPDB0

CamPort™ B Data Bit 0

91

Out

CPSEL

CamPort™ Select Status - When this output is low, the data from CamPort™ A is being

used, when this output is high, the data from CamPort™ B is being used. This pin is

controlled by Bit 3 of the Configuration Register (sub-address = 0x00)

.

44

In

RSTN

Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known

state. When this input is high, the chip can operate.

11

Out

YY7

Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When

CCSEL is high this bus carries multiplexed luminance and chrominance data

10

Out

YY6

Luminance Out bit 6

9

Out

YY5

Luminance Out bit 5

6

Out

YY4

Luminance Out bit 4

5

Out

YY3

Luminance Out bit 3

4

Out

YY2

Luminance Out bit 2

3

Out

YY1

Luminance Out bit 1

2

Out

YY0

Luminance Out bit 0

23

Out

UV7

Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data.

When CCSEL is high this bus carries a constant value of 0x80 (128).

22

Out

UV6

Chrominance Out bit 6

21

Out

UV5

Chrominance Out bit 5

20

Out

UV4

Chrominance Out bit 4

17

Out

UV3

Chrominance Out bit 3

16

Out

UV2

Chrominance Out bit 2

15

Out

UV1

Chrominance Out bit 1

14

Out

UV0

Chrominance Out bit 0

24

Out

CLK2

Clock Out 2X - This clock runs at twice the pixel rate

27

Out

CLK1

Clock Out 1X - This clock runs at the pixel rate.

34

In

OUTEN

Output Enable - When this input is low, the signals YY[7..0], UV[7..0], HSYNC, VSYNC,

CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is high,

these signals are high-impedance.

SIGNALS & PINOUT

* CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table.