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UPD78P9014 数据表(PDF) 21 Page - Renesas Technology Corp

部件名 UPD78P9014
功能描述  MOS INTEGRATED CIRCUIT
PDF  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD78P9014 数据表(HTML) 21 Page - Renesas Technology Corp

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µPD78P9014
19
Mnemonic
Operand
Bytes
Clock
Operation
Flags
ZAC CY
BC
$saddr16
2
6
PC
← PC + 2 + jdisp8 if CY = 1
BNC
$addr16
2
6
PC
← PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
6
PC
← PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
6
PC
← PC + 2 + jdisp8 if Z = 0
BT
saddr. bit, $addr16
4
10
PC
← PC + 4 + jdisp8
if (saddr. bit) = 1
sfr. bit, $addr16
4
10
PC
← PC + 4 + jdisp8 if sfr. bit = 1
A. bit, $addr16
3
8
PC
← PC + 3 + jdisp8 if A. bit = 1
PSW. bit, $addr16
4
10
PC
← PC + 4 + jdisp8 if PSW. bit = 1
BF
saddr. bit, $addr16
4
10
PC
← PC + 4 + jdisp8
if (saddr. bit) = 0
sfr. bit, $addr16
4
10
PC
← PC + 4 + jdisp8 if sfr. bit = 0
A. bit, $addr16
3
8
PC
← PC + 3 + jdisp8 if A. bit = 0
PSW. bit, $addr16
4
10
PC
← PC + 4 + jdisp8 if PSW. bit = 0
DBNZ
B, $addr16
2
6
B
← B – 1, then
PC
← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
C
← C – 1, then
PC
← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
3
8
(saddr)
← (saddr) – 1, then
PC
← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
1
2
No Operation
EI
3
6
IE
← 1 (Enable Interrupt)
DI
3
6
IE
← 0 (Disable Interrupt)
HALT
1
2
Set HALT Mode
STOP
1
2
Set STOP Mode
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control
register (PCC).



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