MP6606

– 60V, 8-CHANNEL LOW-SIDE DRIVER WITH SERIAL INTERFACE

MP6606 Rev. 1.0

MonolithicPower.com

6

3/11/2022

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TIMING CHARACTERISTICS (6)

VIN = 24V, TA = 25°C, unless otherwise noted.

Parameter

Symbol

Condition

Min

Typ

Max

Units

SCK cycle time

t1

100

ns

SCK frequency

This frequency is equal to 1 / t1

0.1

10

MHz

SCK high time

t2

50

ns

SCK low time

t3

50

ns

SCK rising/falling time

50

ns

Set-up time for nSCS

low to SCK rising

t4

30

ns

Set-up time for SDI

valid to SCK rising

t5

15

ns

Hold time for SCK

rising to SDI invalid

t6

10

ns

Disable time for nSCS

high to SDO Hi-Z

t7

75

120

ns

Delay time for SCK

falling to SDO valid

t8

CL < 100pF

10

ns

RESET pulse width

100

ns

TIMING DIAGRAM

Z

X

X

X

V

V

V

X

V

SCK

SDI

SDO

1

2

3

4

5

6

7

Z

nSCS

X

V

V

V

8

Note:

6) Not subject to production testing. Specified by design.