80220 datasheet(21/91 Pages) LSI

21 / 91 page

80220/80221

4-21

MD400159/E

start of packet for 10 Mbps mode is detected when valid

data is detected by the TP squelch circuit. When start of

packet is detected, CRS is asserted as described in the

Controller Interface section.

Refer to the TP squelch

section for 10 Mbps mode for the algorithm for valid data

detection.

3.12 END OF PACKET

3.12.1 100 Mbps

End of packet for 100 Mbps mode is indicated by a the End

of Stream Delimiter (referred to as ESD). The ESD pattern

consists of the two /T/R/ 4B5B symbols inserted after the

end of the packet, as defined in IEEE 802.3 Clause 24 and

shown in Figure 2.

The transmit ESD is generated by the 4B5B encoder and

the /T/R/ symbols are inserted by the 4B5B encoder after

the end of the transmit data packet, as shown in Figure 2.

The receive ESD pattern is detected by the 4B5B decoder

by examining groups of 10 consecutive code bits (two 5B

words) from the descrambler during valid packet reception

to determine if there is an ESD.

If the 10 consecutive code bits from the receiver during

valid packet reception consist of the /T/R/ symbols, the end

of packet is detected, data reception is terminated, CRS

and RX_DV are asserted, and /I/I/ symbols are substituted

in place of the /T/R/ symbols.

If 10 consecutive code bits from the receiver during valid

packet reception do not consist of /T/R/ symbols but

consist of /I/I/ symbols instead, then the packet is consid-

ered to have been terminated prematurely and abnor-

mally. When this premature end of packet condition is

detected, RX_ER is asserted for the nibble associated with

the first /I/ symbol detected and then CRS and RX_DV are

deasserted.

Premature end of packet condition is also

indicated by setting the bad ESD bit in the MI serial port

Status Output register.

3.12.2 10 Mbps

The end of packet for 10 Mbps mode is indicated with the

SOI (Start of Idle) pulse. The SOI pulse is a positive pulse

containing a Manchester code violation inserted at the end

of every packet .

The transmit SOI pulse is generated by the TP transmitter

and inserted at the end of the data packet after TX_EN is

deasserted. The transmitted SOI output pulse at the TP

output is shaped by the transmit waveshaper to meet the

pulse template requirements specified in

IEEE 802.3

Clause 14 and shown in Figure 6.

The receive SOI pulse is detected by the TP receiver by

sensing missing data transitions. Once the SOI pulse is

detected, data reception is ended and CRS and RX_DV

are deasserted.

0 BT

4.5 BT

6.0 BT

+50 mV

45.0 BT

4.5 BT

2.5 BT

2.25 BT

0.25 BT

0.5 V/ns

3.1 V

–50 mV

585 mV

–3.1 V

585 mV sin(2

(t/1BT))

0.25 BT and

2.25

2.5 BT

***

Figure 6. SOI Output Voltage Template - 10 Mbps

80220 数据表(PDF) 21 Page - LSI Computer Systems

80220 数据表(HTML) 21 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

数据表下载