80220 datasheet(13/91 Pages) LSI

13 / 91 page

80220/80221

4-13

MD400159/E

When the end of packet is detected, CRS and RX_DV are

deasserted, and RXD[3:0] is held low. CRS and RX_DV

also stay deasserted if the device is in the Link Fail State.

RX_ER is a receive error output which is asserted when

certain errors are detected on a data nibble. RX_ER is

asserted on the falling edge of RX_CLK for the duration of

that RX_CLK clock cycle during which the nibble contain-

ing the error is being outputted on RXD[3:0].

The collision output, COL, is asserted whenever the colli-

sion condition is detected.

3.3.3 MII - 10 Mbps

10 Mbps operation is identical to the 100 Mbps operation

except, (1) TX_CLK and RX_CLK clock frequency is

reduced to 2.5 MHZ, (2) TX_ER is ignored, (3) RX_ER is

disabled and always held low, and (4) receive operation is

modified as follows: On the receive side, when the squelch

circuit determines that invalid data is present on the TP

inputs, the receiver is idle. During idle, RX_CLK follows

TX_CLK, RXD[3:0] is held low, and CRS and RX_DV are

deasserted. When a start of packet is detected on the TP

receive inputs, CRS is asserted and the clock recovery

process starts on the incoming TP input data. After the

receive clock has been recovered from the data, the

RX_CLK is switched over to the recovered clock and the

data valid signal RX_DV is asserted on a falling edge of

RX_CLK. Once RX_DV is asserted, valid data is clocked

out on RXD[3:0] on falling edges of the RX_CLK clock. The

RXD[3:0] data has the same packet structure as the

TXD[3:0] data and is formatted on RXD[3:0] as specified

in IEEE 802.3 and shown in Figure 3. When the end of

packet is detected, CRS and RX_DV are deasserted.

CRS and RX_DV also stay deasserted as long as the

device is in the Link Fail State.

3.3.4 FBI - 100 Mbps

The Five Bit Interface (also referred to as the FBI) is a five

bit wide interface that is produced when the 4B5B encoder/

decoder is bypassed. The FBI is primarily used for repeat-

ers or Ethernet controllers which have integrated encoder/

decoders.

The FBI is identical to the MII except, (1) the FBI data path

is five bits wide, not nibble wide like the MII, (2) TX_ER pin

is reconfigured to be the fifth transmit data bit, TXD4, and

(3) RX_ER pin is reconfigured to be the fifth receive data

bit RXD4, (4) CRS is asserted as long as the device is in

the Link Pass State, (5) COL is not valid, (6) RX_DV is not

valid, and (7) TX_EN is ignored.

3.3.5 FBI - 10 Mbps

The FBI is not available in 10 Mbps mode.

3.3.6 Selection Of MII Or FBI

The FBI is automatically enabled when the 4B5B encoder/

decoder is bypassed. Bypassing the encoder/decoder

passes the 5B symbols between the receiver/transmitter

directly to the FBI without any alteration or substitutions

noted in the Encoder and Decoder sections. The 4B5B

encoder/decoder can be bypassed by setting the bypass

encoder bit in the MI serial port Configuration 1 register.

When the FBI is enabled, it may also be desirable to

bypass the scrambler/descrambler and disable the inter-

nal CRS loopback function. The scrambler/descrambler

can be bypassed by setting the bypass scrambler bit in the

MI serial port Configuration 1 register. The internal CRS

loopback can be disabled by setting the TX_EN to CRS

loopback disable bit in the MI serial port Configuration 1

3.3.7 MII Disable

The MII and FBI inputs and outputs can be disabled by

setting the MII disable bit in the MI serial port Control

ignored, the MII/FBI outputs are placed in high impedance

state, and the TP output is high impedance.

If the MI address lines, MDA[4:0], are pulled high during

reset or powerup, the 80220/80221 powers up and resets

with the MII and FBI disabled. Otherwise, the 80220/

80221 powers up and resets with the MII and FBI enabled.

3.3.8 Receive Output High Impedance Control

The RX_EN/JAM pin can be configured to be RX_EN, a

high impedance control for the receive controller output

signals, by setting the R/J Configuration select bit in the MI

serial port Configuration 2 register.

When this pin is

configured to be RX_EN and is deasserted active low, the

following outputs will be placed in the high impedance

state: RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL.

3.3.9 TX_EN to CRS Loopback Disable

The internal TX_EN to CRS loopback can be disabled by

appropriately setting the TXEN to CRS loopback disable

bit in the MI serial port Configuration 1 register.

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