M24C64-RBN3SLASHP datasheet(9/34 Pages) STMICROELECTRONICS

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M24128, M24C64, M24C32

Signal description

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2.3

Supply voltage (VCC)

2.3.1

Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10).

In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line

with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS

package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (tW).

2.3.2

Internal device reset

In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)

circuit is included. At Power-up (continuous rise of VCC), the device does not respond to any

instruction until VCC has reached the Power On Reset threshold voltage (this threshold is

lower than the minimum VCC operating voltage defined in Table 9 and Table 10).

When VCC has passed the POR threshold, the device is reset and is in Standby Power

mode.

2.3.3

Power-down

At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal

operating voltage to below the Power On Reset threshold voltage, the device stops

responding to any instruction sent to it.

During Power-down, the device must be deselected and in the Standby Power mode (that is

there should be no internal Write cycle in progress).

Figure 4.

Maximum RP value versus bus parasitic capacitance (C) for an I

2C bus

AI01665b

VCC

SDA

MASTER

SCL

100

C (pF)

1000

fc = 400kHz

fc = 100kHz

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