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AX88170L 数据表(PDF) 21 Page - ASIX Electronics Corporation |
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AX88170L 数据表(HTML) 21 Page - ASIX Electronics Corporation |
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21 / 39 page  ASIX ELECTRONICS CORPORATION 21 CONFIDENTIAL AX88170 PRELIMINARY 6.4.5 MII Timing of PHY mode Ttclk Ttch Ttcl TXCLK(out) Tts Tth TXD<3:0>(in) TXEN(in) Trclk Trch Trcl RXCLK(out) Trs Trh RXD<3:0>(out) RXDV(out) Tcrsh CRS(out) Symbol Description Min Typ. Max Units Ttclk Cycle time(100Mbps) - 40 - ns Ttclk Cycle time(10Mbps) - 400 - ns Ttch high time(100Mbps) 14 - 26 ns Ttch high time(10Mbps) 140 - 260 ns Trch low time(100Mbps) 14 - 26 ns Trch low time(10Mbps) 140 - 260 ns Tts TXD, TXEN setup to TXCLK high 15 - - ns Tth TXD, TXEN hold to TXCLK high 0 - - ns Trclk Cycle time(100Mbps) - 40 - ns Trclk Cycle time(10Mbps) - 400 - ns Trch high time(100Mbps) 14 - 26 ns Trch high time(10Mbps) 140 - 260 ns Trcl low time(100Mbps) 14 - 26 ns Trcl low time(10Mbps) 140 - 260 ns Trv RXD, RXDV valid to RXCLK high 10 - - ns Trh RXCLK high to RXD, RXDV invalid 10 - - ns Tcrsh RXCLK high to CRS invalid 10 - - ns |
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