AX88170L datasheet(9/39 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88170

PRELIMINARY

2.4 RMII interface signal pins (PHY mode)

When /S_RMII=0 and /S_MAC=1

SIGNAL

TYPE

PIN NO.

DESCRIPTION

RXD[1:0]

27, 26

Receive Data : Basically RXD[1:0] is transformed from TXD[1:0] of MAC

mode of RMII interface.

CRS_DV

Carrier Sense _ Data Valid : Basically CRS_DV is transformed of TX_EN

from MAC mode of RMII interface.

TXD[1:0]

I/PU

19, 18

Transmit Data : Basically TXD[1:0] is transformed from RXD[1:0] of MAC

mode of RMII interface.

TX_EN

I/PD

Transmit Enable : Basically TX_EN is transformed from RX_DV from MAC

mode of RMII interface.

REF_CLK

Reference clock : The input is a continue clock at 50Mhz for timing

reference with RMII interface.

Tab – 5 RMII interface signal pins (PHY mode)

2.5 Miscellaneous pins group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

25M_XIN

CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60% duty

cycle. ( See application note also )

Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be

connected across 25M_XIN and 25M_XOUT.

25M_XOUT

Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be

connected across 25M_XIN and 25M_XOUT. If a single-ended external

clock is connected to 25M_XIN, the crystal output pin should be left

floating.

48M_XIN

48Mhz CMOS Clock In : Typical a 48Mhz clock, +/- 500 ppm, 40%-60% duty

cycle. ( See application note also )

48Mhz Crystal Oscillator Input: Typical a 48Mhz crystal, +/- 100 ppm can be

connected across 48M_XIN and 48M_XOUT.

48M_XOUT

48Mhz Crystal Oscillator Output: Typical a 48Mhz crystal, +/- 100 ppm can

be connected across 48M_XIN and 48M_XOUT. If a single-ended external

clock is connected to 48M_XIN, the crystal output pin should be left

floating.

25M_CLKO

Clock Output : This clock is source from 25M_XIN.

/RST

I/PD

Reset:

Reset is active low then place AX88170 into reset mode immediately.

During Ris ing edge the AX88170 loads the EEPROM data.

/S_RMII

I/PU

Set to RMII mode:

0: RMII mode is selected.

1: MII mode is selected. (default)

/S_MAC

I/PD

Set MII/RMII interface to MAC mode:

0: MAC mode is selected. (default)

1: PHY mode is selected.

/S_FDPX

I/PD

Set duplex mode when PHY mode is selected or When S_EXT is set and

MAC mode is selected:

0: full-duplex mode is selected. (default)

1: half-duplex mode is selected.

S_EXT

I/PD

Select where duplex mode is sourced from when MAC mode:

0: duplex mode depands on internal register. (default)

1: duplex mode depands on external signal /S_FDPX

SPD_UP

The setting is enable speed up test mode:

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