ADP1653

Rev. A | Page 19 of 24

4.5

0

0

HPLED CURRENT, 2 LED CASE (mA)

500

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

100

200

300

400

2.2μH + 20%

3.3μH+ 20%

Figure 31. Minimum Output Capacitance for L = 3.3 μH + 20% and

L = 2.2 μH + 20% for Two-LED Designs

4.0

0

0

500

HPLED CURRENT, 1 LED CASE (mA)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

50

100

150

200

250

300

350

400

450

2.2μH + 20%

Figure 32. Minimum Output Capacitance for L = 2.2 μH + 20%

for One-LED Design

5.0

0

01

DC BIAS (V)

2

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2468

10

–40°C (10V)

+85°C (10V)

Figure 33. DC Bias Characteristic of a 10 V, 4.7 μF Ceramic Capacitor

PCB BOARD LAYOUT

Good PCB layout is important to maximize efficiency and to

minimize noise and electromagnetic interference (EMI). An

example PCB layout is shown in Figure 34. Refer to the

following guidelines for adjustment to the suggested layout.

The high current paths are shown in Figure 35. Place components

that are on high current paths first. To minimize large current

loops, place the input capacitor, inductor, Schottky diode, and

output capacitor as close as possible to each other and to the

ADP1653 using wide tracks (use shapes where possible).

Use separate analog and power ground planes. The analog ground

plane is used to ground the SETI, SETT, and SETF resistors and

for any digital connections (that is, INTF = 0 = AGND).

Use the power ground plane to ground the power components.

Connect the input capacitor, output capacitor, and the PGND pin

(Pin 12) to the PGND plane. If it is not possible to make the PGND

plane continuous, use a number of low inductance vias to connect

the planes. Connect the AGND and PGND planes at the paddle

or close to the paddle of the ADP1653.

The SETI, SETT, and SETF resistors set a small reference current

that generates the LED current. To minimize noise and current

error, connect the SETI, SETT, and SETF resistors as close as

possible to the ADP1653. Connect the other end of the resistors

directly to the AGND plane.

Connect the output capacitor to the high power LED(s), using

a wide, low resistance trace. Connect the bottom of the LED string

back to the HPLED pin (Pin 9) with a wide trace. The GND pin

(Pin 8) is connected to the source of the current regulator NFET.

Ensure that there is a low impedance back to the battery for the

high power LED current by connecting the GND pin to the PGND

plane with a low impedance via(s) close to the GND pin.

The OUT pin is used for soft start and contains a comparator

for overvoltage protection. Connect the output capacitor back

to the OUT pin (Pin 7) with a direct trace. The trace does not

need to be wide.