| 数据搜索系统,热门电子元器件搜索 |
|
MAS6180 数据表(PDF) 2 Page - Micro Analog systems |
|
|
|||||||||||||||||||||||||||||
MAS6180 数据表(HTML) 2 Page - Micro Analog systems |
|
2 / 9 page ![]() 2 (9) DA6180.001 27 December, 2006 MAS6180 PAD LAYOUT PDN AON RFIM RFIP DEC VSS AGC QI VDD QOP OUT 1070 µ µ µ µ m QOM MAS6180Ax, x = 1, 2, 5 VSS pad bonded first! DIE size = 1.07 mm x 1.37 mm; PAD size = 80 µm x 80 µm Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Name X-coordinate Y-coordinate Note Power Supply Voltage VDD 152 µm 1137 µm Positive Quartz Filter Output for Crystal QOP 152 µm 1002 µm Negative Quartz Filter Output for Crystal QOM 152 µm 815 µm 1 Quartz Filter Input for Crystal and External Compensation Capacitor QI 152 µm 629 µm AGC Capacitor AGC 152 µm 443 µm Receiver Output OUT 152 µm 257 µm 2 Demodulator Capacitor DEC 915 µm 265 µm AGC On Control AON 915 µm 451 µm 3 Power Down PDN 915 µm 636 µm 4 Positive Receiver Input RFIP 915 µm 824 µm 5 Negative Receiver Input RFIM 915 µm 1010 µm 5 Power Supply Ground VSS 915 µm 1158 µm Notes: 1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |