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LMP7701 数据表(PDF) 15 Page - National Semiconductor (TI) |
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LMP7701 数据表(HTML) 15 Page - National Semiconductor (TI) |
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15 / 22 page ![]() Application Information LMP7701/LMP7702/LMP7704 The LMP7701/LMP7702/LMP7704 are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each with CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP7701/LMP7702/ LMP7704 have a very low input bias current of only ±200 fA at room temperature. The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40˚C to 125˚C makes the LMP7701/LMP7702/LMP7704 excellent choices for low volt- age precision applications with extensive temperature re- quirements. The LMP7701/LMP7702/LMP7704 have only ±37 µV of typi- cal input referred offset voltage and this offset is guaranteed to be less than ±500 µV for the single and ±520 µV for the dual and quad, over temperature. This minimal offset voltage allows more accurate signal detection and amplification in precision applications. The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/ give the LMP7701/ LMP7702/LMP7704 superiority for use in sensor applica- tions. Lower levels of noise introduced by the amplifier mean better signal fidelity and a higher signal-to-noise ratio. National Semiconductor is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. The LMP7701 is offered in the space saving 5-Pin SOT23 package, the LMP7702 comes in the 8-pin MSOP, and the LMP7704 is offered in the 14-Pin TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable electronics. CAPACITIVE LOAD The LMP7701/LMP7702/LMP7704 can each be connected as a non-inverting unity gain follower. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the amplifier’s output impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be either underdamped or it will oscillate. In order to drive heavier capacitive loads, an isolation resis- tor, R ISO,in Figure 1 should be used. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the pole caused by C L is no longer in the feedback loop. The larger the value of R ISO, the more stable the output voltage will be. If values of R ISO are sufficiently large, the feedback loop will be stable, independent of the value of C L. However, larger values of RISO result in reduced output swing and reduced output current drive. INPUT CAPACITANCE CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP7701/ LMP7702/LMP7704 enhance this performance by having the low input bias current of only ±200 fA, as well as, a very low input referred voltage noise of 9 nV/ . In order to achieve this a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7701/ LMP7702/ LMP7704. The typical value of this input capaci- tance, C IN, for the LMP7701/LMP7702/LMP7704 is 25 pF. The input capacitance will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the fre- quency increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain peaking. In order to compensate for the input capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The DC gain of the circuit shown in Figure 2 is simply –R 2/R1. For the time being, ignore C F. The AC gain of the circuit in Figure 2 can be calculated as follows: 20127321 FIGURE 1. Isolating Capacitive Load 20127344 FIGURE 2. Compensating for Input Capacitance www.national.com 15 |
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