5 (18)

DA9116.005

22 November, 2005

REGISTER DESCRIPTION

Register

Address Byte

Data Byte

7

6

5

4

3

2

1

0

msb…lsb

Function

Peak Detector Status

CR4

X

1

0

1

1

R/W

X

X

Output code

00000000

00000001

00000010

00000011

No overload

Right overload

Left overload

Both overload

Peak Detector Reference

CR3

X

1

1

0

0

R/W

X

X

Input code

11111111

11111110

11111101

•

•

00000010

00000001

00000000

DAC output

VREF(255)

VREF(254)

VREF(253)

•

•

VREF(2)

VREF(1)

VREF(0)

Note 1

Left Channel Gain

CR2

X

1

1

0

1

R/W

X

X

Input code

11111111

11111110

11111101

•

•

11100000

00000010

00000001

00000000

Gain dB

+15.5

+15.0

+14.5

•

•

0.0

-111.0

-111.5

mute

Right Channel Gain

CR1

X

1

1

1

0

R/W

X

X

Input code

11111111

11111110

11111101

•

•

11100000

00000010

00000001

00000000

Gain dB

+15.5

+15.0

+14.5

•

•

0.0

-111.0

-111.5

mute

Test, CR5

X

1

1

1

1

R/W

X

X

Reserved

Both Channel Gains

X

1

0

0

1

W

X

X

Write to both gain registers

Note 1. Reference voltage is calculated from VREF(CODE)=(0.16+0.0133*CODE)*VDD

Address byte bits:

•

Bit 2 is read/write bit (1=read, 0=write).

•

X is don’t care, recommended high for low

power.

Data byte bits:

•

All registers get their default value 00Hex except

CR3 which gets FFHex during power-on reset.

•

Default value for all bits is zero (00hex).