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MAS9116ASBA 数据表(PDF) 11 Page - Micro Analog systems |
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MAS9116ASBA 数据表(HTML) 11 Page - Micro Analog systems |
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11 / 18 page ![]() 11 (18) DA9116.005 22 November, 2005 Serial Interface Timing APPLICATION INFORMATION Power supply connection and decoupling To get the best performance of the chip all digital activities should be avoided during analog signal processing. Important: Analog (AVDD) and digital (DVDD) supply voltage pins should be always connected directly together to keep them in the same voltage potential. No resistor is allowed in connection between AVDD and DVDD (see supply voltage connection circuit in the Application Note 1 on the next page). Otherwise possible voltage difference could trigger latch-up phenomenom which can damage the device. Due to the same reason also the digital control input voltages should not exceed supply and ground voltages as specified in absolute maximum rating specifications on page 6. These requirements are valid also during the startup when supply voltages are applied. Low noise supply voltages should be used for high quality audio. Supply decoupling capacitors must be located as close to MAS9116 as possible. Opamp produced output offset voltage Opamp non-idealities in input offset voltage and in input bias current both produce offset voltage to the output. Since this offset voltage is gain dependent the gain change step can produce dc voltage steps to the output. To achieve the best audio performance it is recommended to use opamps which have both low input offset voltage and low input bias current characteristics. Burr-Brown OP277 has excellent offset and bias and no trimming is needed. Also Analog Devices OP1177 and AD8610 offer very good offset performance. See table below for these and other recommended op-amps. Manufacturer Part Number Typical Output Offset at Maximum Gain (mV) Analog Devices OP275 8.5 Analog Devices OP1177 0.51 Analog Devices AD8610 1.49 Texas Instruments (BurrBrown) OP277 0.23 Linear LT1793 18.5 On-Semi, ST Microelectronics MC33078 28.4 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 TWHC TWLC TRC TFC TSSLCH THCSH TSDCH THCHD TDCLD TDSZ THLCHS TSSHCH CCLK DATA (IN) DATA (OUT) 9 10 11 12 13 14 15 16 XCS ADDRESS BYTE DATA BYTE |
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